This invention relates to circuitry for handling serial data signals such as high-speed serial data signals that may be used for conveying information between various devices (e.g., various integrated circuits) in a system (such as on a printed circuit board). Although the circuitry of this invention can be constructed from several discrete circuit components, a more typical implementation is in a single integrated circuit. Such an integrated circuit implementation of the invention can be in any of a wide range of devices such as microprocessors, microcontrollers, programmable logic devices (“PLDs”), field-programmable gate arrays (“FPGAs”), application-specific integrated circuits (“ASICs”), structured ASICs, and many other types of integrated circuits. (For convenience herein, PLDs, FPGAs, and all other devices of that general kind will be referred to generically as PLDs.)
Various serial data signal communication protocols employ a few more bits than the minimum number needed to actually represent the data being communicated. Such extra bits may be used for such purposes as indicating word alignment boundaries for block synchronization, parity checking, error correction coding, ensuring that there is no net direct current (“DC”) in the data signal, etc. For example, several industry-standard codes have been or are being developed that transmit 66 bits for every 64 bits of “actual,” “real,” or “payload” data. Such a signalling or communication protocol may be referred to as 64B66B coding or the like. Another example of this type of code is 64B67B coding, in which 67 bits are transmitted for every 64 bits of actual data content. Still another example is 128B130B coding, which transmits 130 bits for every 128 bits of real data. For convenience herein, all bits that are transmitted in addition to the actual data bits will sometimes be referred to as extra bits of protocol encoding or the like. Thus in 64B66B encoding, the two extra bits beyond the 64 actual data bits may be referred to as extra protocol bits or the like. To distinguish the 64 actual data bits from those two extra protocol bits, the actual data bits may sometimes be referred to herein as the actual data bits or the like.
When a circuit device receives a serial data signal from another device, the receiving device (“the receiver”) very often needs to convert that serial data to a more parallel form at a relatively early stage in the handling of the received information. For example, the receiver may need to convert the purely serial incoming signal to successive “bytes” or “words” of parallel data. (The term “byte” will sometimes be used as generic term for all such groups of parallel bits, regardless of how many bits are in such a group.) For example, each such byte may include (in parallel) a respective group of 8, 10, 16, 20, 32, 40, or more successive bits from the received serial data signal. In addition to thus converting the received data from serial to parallel form, other objectives of such early handling of the incoming data may be (1) to discard or at least identifiably separate any extra protocol encoding bits from the actual data bits, (2) to “align” the parallel data bits with predetermined “boundaries” for valid bytes of data, etc.
It can be a challenging task to accomplish all of the foregoing functions efficiently, especially for serial data signals that are received at very high data rates (e.g., 10 gigabits per second and higher), and even more especially in the case of “general purpose” circuitry (such as a PLD) that is intended to be able to handle any of several different communication protocols in different possible uses of the PLD.